▲ 163 ▼ Linux geeks cheer as Arm wrestles x86 • The Register (www.theregister.com) submitted 2 years ago by sabreW4K3@lazysoci.al to c/linux@lemmy.ml 58 comments fedilink hide all child comments
[+] 737@lemmy.blahaj.zone 4 points 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago (1 child) All else being equal, a complex decoding pipeline does reduce the efficiency of a processor. It’s likely not the most important aspect, but eventually there will be a point where it does become an issue once larger efficiency problems are addressed. permalink fedilink source parent hideshow 2 child comments replies: [+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago (1 child) Well, not exactly. You have to remove instructions at some point. That’s what Intel’s x86-S is supposed to be. You lose some backwards compatibility but they’re chosen to have the least impact on most users. permalink fedilink source parent hideshow 2 child comments replies: [+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago Instruction decoding takes space and power. If there are fewer, smaller transistors dedicated to the task it will take less space and power. permalink fedilink source parent
[–] bamboo@lemm.ee 1 point 2 years ago (1 child) All else being equal, a complex decoding pipeline does reduce the efficiency of a processor. It’s likely not the most important aspect, but eventually there will be a point where it does become an issue once larger efficiency problems are addressed. permalink fedilink source parent hideshow 2 child comments replies: [+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago (1 child) Well, not exactly. You have to remove instructions at some point. That’s what Intel’s x86-S is supposed to be. You lose some backwards compatibility but they’re chosen to have the least impact on most users. permalink fedilink source parent hideshow 2 child comments replies: [+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago Instruction decoding takes space and power. If there are fewer, smaller transistors dedicated to the task it will take less space and power. permalink fedilink source parent
[+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago (1 child) Well, not exactly. You have to remove instructions at some point. That’s what Intel’s x86-S is supposed to be. You lose some backwards compatibility but they’re chosen to have the least impact on most users. permalink fedilink source parent hideshow 2 child comments replies: [+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago Instruction decoding takes space and power. If there are fewer, smaller transistors dedicated to the task it will take less space and power. permalink fedilink source parent
[–] bamboo@lemm.ee 1 point 2 years ago (1 child) Well, not exactly. You have to remove instructions at some point. That’s what Intel’s x86-S is supposed to be. You lose some backwards compatibility but they’re chosen to have the least impact on most users. permalink fedilink source parent hideshow 2 child comments replies: [+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago Instruction decoding takes space and power. If there are fewer, smaller transistors dedicated to the task it will take less space and power. permalink fedilink source parent
[+] 737@lemmy.blahaj.zone 1 point 2 years ago* (last edited 1 year ago) (1 child) [deleted] permalink fedilink source parent hideshow 2 child comments replies: [–] bamboo@lemm.ee 1 point 2 years ago Instruction decoding takes space and power. If there are fewer, smaller transistors dedicated to the task it will take less space and power. permalink fedilink source parent
[–] bamboo@lemm.ee 1 point 2 years ago Instruction decoding takes space and power. If there are fewer, smaller transistors dedicated to the task it will take less space and power. permalink fedilink source parent